TMD2621 datasheet(25/59 Pages) OSRAM

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[v4-00] 2023-Apr-12

TMD2621 − Register O ver view

LDR0_CFG Register (Address 0x9A)

Figure 35:

LDR0_CFG Register

EYE_SAFETY_CFG Register (Address 0x9E)

Figure 36:

EYE_SAFETY_CFG Register

Addr: 0x9A

LDR0_CFG

Bit

Bit Name

Default

Access

Bit Description

Reserved

Reserved. Must be set to default value.

6EN_LDR_0

Enables the LDR0.

5:4

ISINK_LSB

This field sets VCSEL drive current resolution.

Value

VCSEL Drive Current Resolution

0.5mA

1.0mA

1.5mA

2.0mA

3:0

PLDRIVE0

0010

This field sets the drive current of the VCSEL driver 0.

The formula is shown below:

Drive Current 0=(PLDRIVE0+1) x ISINK_LSB.

The drive current should be configured within the range

of 7mA ~10mA.

The values are the nominal current. The actual current

through the VCSEL is factory trimmed to normalize the IR

intensity.

Addr: 0x9E

EYE_SAFETY_CFG

Bit

Bit Name

Default

Access

Bit Description

EYE_SAFETY_CHKS_ENAB

Enables VDD and VSS short check for

PLDRIVE0, and also the analog watch dog

timer.

Eye safety runs only once at the beginning

when PON and PEN are enabled.

DISABLE_PROX_ON_WD_FAIL

Disable the high side switch when the eye

safety watch dog expires.

5:0

Reserved

Reserved. Must be set to default value.

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