LM5100A datasheet(11/15 Pages) NSC

11 / 15 page

Timing Diagram

Layout Considerations

The optimum performance of high and low-side gate drivers

cannot be achieved without taking due considerations during

circuit board layout. Following points are emphasized.

Low ESR / ESL capacitors must be connected close to

the IC, between VDD and VSS pins and between the HB

and HS pins to support the high peak currents being

drawn from VDD during turn-on of the external MOS-

FET.

To prevent large voltage transients at the drain of the top

MOSFET, a low ESR electrolytic capacitor must be con-

nected between MOSFET drain and ground (VSS).

In order to avoid large negative transients on the switch

node (HS pin), the parasitic inductances in the source of

top MOSFET and in the drain of the bottom MOSFET

(synchronous rectifier) must be minimized.

Grounding Considerations:

a) The first priority in designing grounding connections

is to confine the high peak currents that charge and

discharge the MOSFET gate into a minimal physical

area. This will decrease the loop inductance and mini-

mize noise issues on the gate terminal of the MOSFET.

The MOSFETs should be placed as close as possible to

the gate driver.

b) The second high current path includes the boot-

strap capacitor, the bootstrap diode, the local ground

referenced bypass capacitor and low-side MOSFET

body diode. The bootstrap capacitor is recharged on a

cycle-by-cycle basis through the bootstrap diode from

the ground referenced VDD bypass capacitor. The re-

charging occurs in a short time interval and involves high

peak current. Minimizing this loop length and area on the

circuit board is important to ensure reliable operation.

Power Dissipation Considerations

The total IC power dissipation is the sum of the gate driver

losses and the bootstrap diode losses. The gate driver

losses are related to the switching frequency (f), output load

capacitance on LO and HO (C

L), and supply voltage (VDD)

and can be roughly calculated as:

DGATES =2 • f • CL • VDD

There are some additional losses in the gate drivers due to

the internal CMOS stages used to buffer the LO and HO

outputs. The following plot shows the measured gate driver

power dissipation versus frequency and load capacitance. At

higher frequencies and load capacitance values, the power

dissipation is dominated by the power losses driving the

output loads and agrees well with the above equation. This

plot can be used to approximate the power losses due to the

gate drivers.

Gate Driver Power Dissipation (LO + HO)

DD = 12V, Neglecting Diode Losses

20203105

The bootstrap diode power loss is the sum of the forward

bias power loss that occurs while charging the bootstrap

capacitor and the reverse bias power loss that occurs during

reverse recovery. Since each of these events happens once

per cycle, the diode power loss is proportional to frequency.

20203104

FIGURE 3.

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