EM6620WS27 datasheet(28/56 Pages) EMMICRO

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EM6620

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8.3 MSC-Modes

The millisecond counter can have many different modes of operation. The most common are :

- CPU controlled start and stop.

- CPU controlled start and PA[3] controlled stop.

- Port A terminal PA[3] controlled start and stop mode.

- Pulse width measurement of port A terminal PA[3] input signals.

All these different modes are controlled with the bits in the registers RegMSCCntl1 and RegMSCCntl2.

The main bits are :

- dT/MSC ;

Pulse-width or start stop measure. This bit only has a action if PA[3] input is chosen. If pulse-

width measure is selected, the counter starts with the first active edge on PA[3] and stops with

the next inverse edge (sets RunEn = 0). If MSC measure selected, the counter starts with the

first active PA[3] edge, stops on the next, restarts on the following etc. It does not reset

RunEn.

- PA3/µP ;

Direct port A terminal PA[3] or CPU (µP) controlled start and stop function. If direct PA[3]

controlled start stop mode is chosen the counter, once enabled by setting RunEn/Stop = 1,

starts counting on the first active edge seen on PA[3]. It stops counting depending on the

dT/MSC bit either on the next inverse edge or on the next active edge. If µP is chosen, the

counter starts and stops depending on bit RunEn/Stop.

- RunEn/Stop; In CPU mode this bit starts or stops the counter. In PA3 mode it enables the counter which will

start with the next event on port A terminal PA[3]. If dT and PA3 mode, the RunEn gets reset

with the second active PA[3] edge.

- PA3Edge ;

This bit selects the active PA[3] edge which will trigger the dT/MSC selected measurement

mode. It has no effect if PA3/µP=0. Default 0 is negative edge.

8.4 Mode selection

Before using, the MSC counter needs to be reset by setting bit ResMSC to ‘1’. This bit is automatically reset

thereafter. Then select the IRQ frequency and the counting mode. Now the RunEn can be set to ‘1’ . To display

the counter value during run you may only want to read the MSB (1/10 sec) digit ,driven by IRQ or with polling,

and fully read the MSC value only once the counter is stopped. The counter data registers are read only. Any

Reset (system reset, POR, watchdog) is setting the MSC into stop mode and clears the counter registers.

• CPU controlled Start and Stop

As soon as the CPU writes the start bit RunEn/Stop=1 the counter starts up counting until the CPU clears the

start bit. The bit PA3/uP is ‘0’ for this mode.

Figure 19. CPU controlled Start Stop

Counting

Stop

Start

Counter

RunEn/Stop

CPU write

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