EM6620WS27 datasheet(27/56 Pages) EMMICRO

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EM6620

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8. Millisecond Counter

The EM6620 has a built-in millisecond binary coded decimal counter. It can be used to measure the time

elapsed between two events (hardware or software events). With a system clock of 32kHz, the counter

generates every 1/10 second or every second an interrupt request.

The counter value read on registers RegMSCDataL, RegMSCDataM and RegMSCDataH is in binary coded

decimal format (000 to 999). To maintain the data integrity for the 3 decimal digits inside BCD[11:0] one must

stop the counter while reading the full 3 digit value.

An overflow flag FlSec is set whenever the counter reached 999. This flag is helpful when the counter is used

in polling mode and twice the same value is read. In this case, if the flag is set to 1, it indicates that the two

readings were 1 second apart, in the case the flag is not set, the two readings must have been very short one

after the other. After every read of RegMSCCntl2 the FlSec gets automatically reset.

The millisecond counter is reset with every system reset. Setting the ResMSC flag located in register

RegMSCCntl1 resets the counter value only. This flag is automatically reset after the write operation. For good

resolution in Pa3-mode use the Ck[14 ] debouncer clock (250us). Or if the 1/1000 sec is not relevant then

choose Ck[10] (4ms) as debouncer clock. Doing so will save power. The debouncer selection is made in

Changing PA3Edge while RunEn=1 or PA3/up=1 may generate a MSC event (start or stop). This behavior is

useful for the - CPU controlled start and PA3 controlled stop - mode, But in general one does all the setup

before starting the counter.

8.1 PA[3] Input for MSC

In hardware Start/Stop mode the counter is triggered with the port A terminal PA[3] input. In this case PA[3] is

debounced with the prescaler Ck[14] (or Ck[10]) clock. The triggering edge selection is made with bit PA3Edge

in register RegMSCCntl2 (default negative edge). The PA[3] input for the millisecond counter is totally

independent of the PA[3] interrupt edge selection and the PA[3] polarity selection for the 10 bit counter.

However the pull-up or pull-down selection is common to all peripheries sharing the port A.

8.2 IRQ from MSC

An Interrupt request IRQMSC is send on either every 1/10 seconds or every second, depending on the bit

IntSel in register RegMSCCntl2. For interrupt handling please refer to the interrupt control section.

Figure 18. MSC Block Diagram

BCD

1/10

Sec

RegMSCCntl1,2

PA3

Debouncer

IRQMSC

RunEn

PA3/uP

dT/MSC

Data Bus

Data

IntSel

1 Sec

1/10 Sec

Ck[10]

Ck[14

PA[3]

Term inal

PA3Internal

NegEdg

PosEdg

PA3Edge

CK1000

FlSecl

DebFreqSel

Start/Stop

Control

dT/MSC

BCD

1/1000

Sec

BCD

1/100

Sec

This signal used

as reference in

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