EM6620WS27 datasheet(37/56 Pages) EMMICRO

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EM6620

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12.3 Free segment allocation

Each segment (SEG[8:1]) terminal outputs the time multiplexed information from its 4 segment data latches.

Data latch 1 outputs during phase1, latch 2 during phase 2, latch 3 during phase 3 and latch 4 during phase 4.

In the case of 3 to 1 multiplexing the phase 4 is not used. This phase information together with the Common

(COM[4:1]), also called Back-planes, outputs defines if a given segment is light or not. COM[1] is on during

phase 1 and off during phase 2,3,4 , COM[2] is on during phase 2 and off during phase 1,3,4 , etc.

For each segment data latch the address location within the LCD address spacing (LCD_15 ... LCD_0 -->

LcdAdr[15:0]) can be user defined.

For each segment data latch the data bus connection (DB[3:0]) can be user defined.

Segment outputs

COM[1]

COM[2]

COM[3]

COM[4]

SEG[1]

DB[0], LCDAdr[0]

DB[1], LCDAdr[0]

DB[2], LCDAdr[0]

DB[3], LCDAdr[0]

SEG[2]

DB[0], LCDAdr[1]

DB[1], LCDAdr[1]

DB[2], LCDAdr[1]

DB[3], LCDAdr[1]

SEG[3]

DB[0], LCDAdr[2]

DB[1], LCDAdr[2]

DB[2], LCDAdr[2]

DB[3], LCDAdr[2]

...

SEG[6]

DB[0], LCDAdr[5]

DB[1], LCDAdr[5]

DB[2], LCDAdr[5]

DB[3], LCDAdr[5]

SEG[7]

DB[0], LCDAdr[6]

DB[1], LCDAdr[6]

DB[2], LCDAdr[6]

DB[3], LCDAdr[6]

SEG[8]

DB[0], LCDAdr[7]

DB[1], LCDAdr[7]

DB[2], LCDAdr[7]

DB[3], LCDAdr[7]

12.4 LCD Registers

Table 12.4.1 Register RegLcdCntl1

Bit

Name

Reset

R/W

Description

CkTripSel1

R/W

LCD multiplier clock select

CkTripSel0

R/W

LCD multiplier clock select

Table 12.4.2 multiplier clock frequency select

CkTripSel0

CkTripSel1

multiplier clock

on 32 KHz operation

Ck[10]

512 Hz

Ck[9]

256 Hz

Ck[8]

128 Hz

Ck[7]

64 Hz

Table 12.4.3 Register RegLcdCntl2

Bit

Name

Reset

R/W

Description

LCDBlank

R/W

LCD segment outputs off

LCDOff

R/W

LCD off (multiplier off)

Lcd4Mux

R/W

4 : 1 multiplexed

LCDExtSupply

(0 on POR)

R/W

external supply for VL1, VL2 and VL3

LCDExtSupply is set to ‘0’ by POR only

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