UPSD3422_V01 datasheet(58/300 Pages) STMICROELECTRONICS

58 / 300 page

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Dual data pointers

UPSD3422, UPSD3433, UPSD3434, UPSD3454

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11.2

Data pointer mode register, DPTM (86h)

The two “background” data pointers, DPTR0 and DPTR1, can be configured to

automatically increment, decrement, or stay the same after a MOVX instruction accesses

the DPTR register. Only the currently selected pointer will be affected by the increment or

decrement. This feature is controlled by the DPTM register defined in Table 15.

The automatic increment or decrement function is effective only for the MOVX instruction,

and not MOVC or any other instruction that uses the DTPR register.

11.2.1

Firmware example

The 8051 assembly code illustrated in Table shows how to transfer a block of data bytes

from one XDATA address region to another XDATA address region. Auto-address

incrementing and auto-pointer toggling will be used.

Table 15.

DPTM: data pointer mode register (SFR 86h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

MD11

MD10

MD01

MD00

Table 16.

DPTM register bit definition

Bit

Symbol

R/W

Definition

7-4

–

Reserved

3-2

MD[11:10]

R,W

DPTR1 mode bits

00: DPTR1 No change

01: Reserved

10: Auto Increment

11: Auto Decrement

1-0

MD[01:00]

R,W

DPTR0 mode bits

00: DPTR0 No change

01: Reserved

10: Auto Increment

11: Auto Decrement

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