SH7041A datasheet(489/923 Pages) RENESAS

No de pièce	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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12.11

Operation

12.11.1

Input Level Detection Operation

If the input conditions set by the ICSR occur on any of the

POE pins, all high-current pins become

high-impedance state.

Falling Edge Detection: When a change from high to low level is input to the

POE pins.

Low-Level Detection: Figure 12.126 shows the low-level detection operation. Sixteen continuous

low levels are sampled with the sampling clock established by the ICSR. If even one high level is

detected during this interval, the low level is not accepted.

Sampling

clock

POE input

PE9/TIOC3B

When low level is sampled

at all points

When high level is sampled

at least once

Flag set

(POE received)

Flag not set

High-impedance

state*

Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/

MRES, PE14/TIOC4C/DACK0/AH,

PE15/TIOC4D/DACK1/

IROOUT) also go to the high-impedance state at the same time.

8/16/128 clock

cycles

Figure 12.126 Low-Level Detection Operation

SH7041A Fiches technique(PDF) 489 Page - Renesas Technology Corp