SH7041A datasheet(487/923 Pages) RENESAS

No de pièce	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

Logo

487 / 923 page

449

12.10.2

Output Level Control/Status Register (OCSR)

The output level control/status register (OCSR) is a 16-bit read/write register that controls the

enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit

is set to 1, the high current pins become high impedance.

OCSR is initialized to H'0000 by an external power-on reset; however, it is not initialized for

manual resets, reset by WDT standby mode, or sleep mode, so the previous data is maintained.

Bit:

OSF

—

OCE

OIE

Initial value:

R/W:

R/(W)*

R/W

Bit:

——

———

—

Initial value:

R/W:

Note: * Only 0 writes are possible to clear the flag.

• Bit 15—Output Short Flag (OSF): This flag indicates that among the three pairs of 2 phase

outputs compared, the outputs of at least one pair have simultaneously become Low level

output.

Bit 15: OSF

Description

Clear condition: By writing 0 to OSF after reading an OSF = 1 (initial value)

Set condition: When any one pair of the 2-phase outputs simultaneously

become Low level

• Bits 14–10—Reserved: These bits always read as 0. The write value should always be 0.

SH7041A Fiches technique(PDF) 487 Page - Renesas Technology Corp