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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SH7041A Fiches technique(PDF) 426 Page - Renesas Technology Corp |
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SH7041A Fiches technique(HTML) 426 Page - Renesas Technology Corp |
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426 / 923 page  388 Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. For DTC/DMA controller activation, clearing can also be done automatically. Figure 12.74 shows the timing for status flag clearing by the CPU. Figure 12.75 shows timing for clearing due to the DTC/DMA controller. Status flag Interrupt request signal Address Write signal φ T1 T2 TSR write cycle TSR address Figure 12.74 Timing of Status Flag Clearing by the CPU Status flag Interrupt request signal Address φ T1 T2 DTC/DMAC read cycle DTC/DMAC write cycle Source address Destination address T1 T2 Figure 12.75 Timing of Status Flag Clearing by DTC/DMAC Activation |
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