IMX6SDLCEC datasheet(119/169 Pages) NXP

119 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

119

4.11.15.1 PCIE_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 200

Ω. 1% precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.11.16 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 84 depicts the timing of the PWM, and Table 78 lists the PWM timing parameters.

Figure 84. PWM Timing

4.11.17 SCAN JTAG Controller (SJC) Timing Parameters

Figure 85 depicts the SJC test clock input timing. Figure 86 depicts the SJC boundary scan timing.

Figure 87 depicts the SJC test access port. Signal parameters are listed in Table 79.

Figure 85. Test Clock Input Timing Diagram

Table 78. PWM Output Timing Parameters

Parameter

Min

Max

Unit

PWM Module Clock Frequency

ipg_clk

MHz

PWM output pulse width high

—

PWM output pulse width low

—

JTAG_TCK

(Input)

VIH

VIL

SJ1

SJ2

SJ3

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