L9026 datasheet(39/60 Pages) STMICROELECTRONICS

39 / 60 page

Parameter

Description

Test condition

Min

Typ

Max

Unit

Input pull up resistor at NCS pin

RNCS

L-input pull-up resistor at NCS pin

VNCS = 0.8 V

KΩ

Input pull down resistor at pin

RCLK

Input pull-down resistor on CLK

VCLK = 2 V

140

KΩ

RSI

Input pull-down resistor on SI

VSI = 2 V

140

KΩ

Output characteristics

VSO(L)

L level output voltage

ISO = -1.5 mA

0.4

VSO(H)

H level output voltage

ISO = 1.5 mA

VDDIO -0.4

VDDIO

ISO(OFF)

Output tristate leakage current

VNCS = VDDIO

VBATT = 0 V

-1

μA

ISO(OFF)

Output tristate leakage current

VNCS =VDDIO

VBATT = VDDIO

-1

μA

Timings

tCSN(lead)

Enable lead time (falling NCS to

rising CLK)

VDDIO = 4.5 V or

VBATT > 7 V

200

tCSN(lag)

Enable lag time (falling CLK to

rising NCS)

VDDIO = 4.5 V or VBATT > 7 V

200

tCSN(td)

Transfer delay time (rising NCS to

falling NCS)

VDDIO = 4.5 V or VBATT > 7 V

650

tSO(en)

Output enable time (falling NCS to

SO valid)

VDDIO = 4.5 V or VBATT > 7 V; CL = 20

pF at MISO pin

200

tSO(dis)

Output disable time (rising NCS to

SO tristate)

VDDIO = 4.5 V or VBATT > 7 V; CL = 20

pF at MISO pin

200

fCLK

Serial clock frequency

VDDIO = 4.5 V or VBATT > 7 V

MHz

tCLK(H)

Serial clock “high” time

VDDIO = 4.5 V or VBATT > 7 V

tCLK(L)

Serial clock “low” time

VDDIO = 4.5 V or VBATT > 7 V

tSI(su)

Data setup time (required time

MOSI to falling CLK)

VDDIO = 4.5 V or VBATT > 7 V

tSI(h)

Data hold time (falling CLK to SI)

VDDIO = 4.5 V or VBATT > 7 V

L9026

SPI electrical specifications

DS13397 - Rev 5

page 39/60

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