JS28F256P30T85 datasheet(85/102 Pages) INTEL

85 / 102 page

1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

Appendix B Flowcharts

Figure 40.

Word Program Flowchart

Program

Suspend

Loop

Start

Write 0x40,

Word Address

Write Data,

Word Address

Read Status

SR[7] =

Full Status

Check

(if desired)

Program

Complete

Suspend?

Yes

WORD PROGRAM PROCEDURE

Repeat for subsequent Word Program operations.

Full Status Register check can be done after each program, or

after a sequence of program operations.

Write 0xFF after the last operation to set to the Read Array

state.

Comments

Bus

Operation

Command

Data = 0x40

Addr = Location to program

Write

Program

Setup

Data = Data to program

Addr = Location to program

Write

Data

Status register data

Read

None

Check SR[7]

1 = WSM Ready

0 = WSM Busy

Idle

None

(Setup)

(Confirm)

FULL STATUS CHECK PROCEDURE

Read Status

Program

Successful

SR[3] =

SR[1] =

SR[4] =

PP Range

Error

Device

Protect Error

Program

Error

If an error is detected, clear the Status Register before

continuing operations - only the Clear Staus Register

command clears the Status Register error bits.

Idle

Bus

Operation

None

Command

Check SR[3]:

1 = V

PP Error

Check SR[4]:

1 = Data Program Error

Comments

Idle

None

Check SR[1]:

1 = Block locked; operation aborted

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