PCF2129 datasheet(84/86 Pages) PHILIPS

84 / 86 page

PCF2129

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Product data sheet

Rev. 7 — 19 December 2014

84 of 86

NXP Semiconductors

PCF2129

Accurate RTC with integrated quartz crystal for industrial applications

26. Figures

Fig 1.

Block diagram of PCF2129 . . . . . . . . . . . . . . . . . .3

Fig 2.

Pin configuration for PCF2129AT (SO20) . . . . . . .4

Fig 3.

Pin configuration for PCF2129T (SO16) . . . . . . . .4

Fig 4.

Position of the stubs from the package assembly

process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 5.

Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 6.

Battery switch-over behavior in standard mode

with bit BIE set logic 1 (enabled) . . . . . . . . . . . . .18

Fig 7.

Battery switch-over behavior in direct switching

mode with bit BIE set logic 1 (enabled) . . . . . . . .19

Fig 8.

Battery switch-over circuit, simplified block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 9.

Battery low detection behavior with bit BLIE set

logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 10. Typical driving capability of VBBS: (VBBS - VDD)

with respect to the output load current IBBS . . . . .22

Fig 11. Power failure event due to battery discharge:

reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 12. Dependency between POR and oscillator . . . . . .24

Fig 13. Power-On Reset (POR) system. . . . . . . . . . . . . .24

Fig 14. Power-On Reset Override (PORO) sequence,

valid for both I2C-bus and SPI-bus . . . . . . . . . . .25

Fig 15. Data flow of the time function. . . . . . . . . . . . . . . .30

Fig 16. Access time for read/write operations . . . . . . . . .31

Fig 17. Alarm function block diagram. . . . . . . . . . . . . . . .32

Fig 18. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .35

Fig 19. WD_CD set logic 1: watchdog activates an

interrupt when timed out . . . . . . . . . . . . . . . . . . .38

Fig 20. Timestamp detection with two push-buttons

on the TS pin (for example, for tamper detection)39

Fig 21. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .45

Fig 22. INT example for SI and MI when TI_TP

is logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Fig 23. INT example for SI and MI when TI_TP

is logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Fig 24. Example of shortening the INT pulse by

clearing the MSF flag . . . . . . . . . . . . . . . . . . . . . .47

Fig 25. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .48

Fig 26. STOP bit functional diagram . . . . . . . . . . . . . . . .49

Fig 27. STOP bit release timing . . . . . . . . . . . . . . . . . . . .50

Fig 28. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .51

Fig 29. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .51

Fig 30. Data transfer overview . . . . . . . . . . . . . . . . . . . . .52

Fig 31. SPI-bus write example . . . . . . . . . . . . . . . . . . . . .53

Fig 32. SPI-bus read example . . . . . . . . . . . . . . . . . . . . .53

Fig 33. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 34. Definition of START and STOP conditions. . . . . .54

Fig 35. System configuration . . . . . . . . . . . . . . . . . . . . . .55

Fig 36. Acknowledgement on the I2C-bus . . . . . . . . . . . .55

Fig 37. Bus protocol, writing to registers . . . . . . . . . . . . .56

Fig 38. Bus protocol, reading from registers . . . . . . . . . .56

Fig 39. Device diode protection diagram of PCF2129 . . .57

Fig 40. IOL on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . .61

Fig 41. IDD as a function of temperature . . . . . . . . . . . . .61

Fig 42. IDD as a function of VDD . . . . . . . . . . . . . . . . . . . .62

Fig 43. Typical IDD as a function of the power

management settings . . . . . . . . . . . . . . . . . . . . . 63

Fig 44. Typical characteristic of frequency with respect to

temperature of PCF2129AT . . . . . . . . . . . . . . . . 65

Fig 45. Typical characteristic of frequency with respect to

temperature of PCF2129T . . . . . . . . . . . . . . . . . 65

Fig 46. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Fig 47. I2C-bus timing diagram; rise and fall times refer to

30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Fig 48. General application diagram . . . . . . . . . . . . . . . . 70

Fig 49. Package outline SOT163-1 (SO20) of

PCF2129AT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Fig 50. Package outline SOT162-1 (SO16) of

PCF2129T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Fig 51. Footprint information for reflow soldering

of SOT163-1 (SO20) of PCF2129AT. . . . . . . . . . 73

Fig 52. Footprint information for reflow soldering

of SOT162-1 (SO16) of PCF2129T. . . . . . . . . . . 74

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