PCF2129 datasheet(68/86 Pages) PHILIPS

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PCF2129

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Product data sheet

Rev. 7 — 19 December 2014

68 of 86

NXP Semiconductors

PCF2129

Accurate RTC with integrated quartz crystal for industrial applications

14.2 I2C-bus timing characteristics

[1]

The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is

held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.

[2]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undefined region of the falling edge of SCL.

[3]

Cb is the total capacitance of one bus line in pF.

[4]

The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows

series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the

maximum tf.

[5]

tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.

[6]

tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.

[7]

Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

Table 82.

I2C-bus characteristics

All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %

and 70 % with an input voltage swing of VSS to VDD (see Figure 47).

Symbol

Parameter

Standard mode

Fast-mode (Fm)

Unit

Min

Max

Min

Max

Pin SCL

fSCL

SCL clock frequency

[1] 0

100

400

kHz

tLOW

LOW period of the SCL clock

4.7

1.3

s

tHIGH

HIGH period of the SCL clock

4.0

0.6

s

Pin SDA/CE

tSU;DAT

data set-up time

250

100

tHD;DAT

data hold time

Pins SCL and SDA/CE

tBUF

bus free time between a STOP

and START condition

4.7

1.3

s

tSU;STO

set-up time for STOP condition

4.0

0.6

s

tHD;STA

hold time (repeated) START

condition

4.0

0.6

s

tSU;STA

set-up time for a repeated START

condition

4.7

0.6

s

rise time of both SDA and SCL

signals

[2][3][4] -

1000

20 + 0.1Cb

300

fall time of both SDA and SCL

signals

[2][3][4] -

300

20 + 0.1Cb

300

tVD;ACK

data valid acknowledge time

[5] 0.1

3.45

0.1

0.9

s

tVD;DAT

data valid time

[6] 300

tSP

pulse width of spikes that must be

suppressed by the input filter

[7] -50

-50

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