AM652X datasheet(209/277 Pages) TI1

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209

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).

Figure 5-72. eMMC/SD/SDIO in - High Speed - Receiver Mode

Figure 5-73. eMMC/SD/SDIO in - High Speed - Transmitter Mode

5.9.5.16.1.3 UHS-I SDR12 Mode

Table 5-72 and Table 5-73 present Timing requirements and Switching characteristics for MMCi - SDR12

in receiver and transmitter mode (see Figure 5-74 and Figure 5-75).

Table 5-72. Timing Requirements for MMCi - SDR12 Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SDR125

tsu(cmdV-clkH)

Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge

9.96

SDR126

th(clkH-cmdV)

Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge

1.67

SDR127

tsu(dV-clkH)

Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock

edge

9.96

SDR128

th(clkH-dV)

Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge

1.67

(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).

Table 5-73. Switching Characteristics for MMCi - SDR12 Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SDR120

fop(clk)

Operating frequency, MMCi_CLK

MHz

SDR121

tw(clkH)

Pulse duration, MMCi_CLK high

18.7

SDR122

tw(clkL)

Pulse duration, MMCi_CLK low

18.7

SDR123

td(clkL-cmdV)

Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition

-13.6

SDR124

td(clkL-dV)

Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]

transition

-13.6

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