AM652X datasheet(210/277 Pages) TI1

210 / 277 page

210

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Specifications

(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).

Figure 5-74. eMMC/SD/SDIO in - High Speed SDR12 - Receiver Mode

Figure 5-75. eMMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode

5.9.5.16.1.4 UHS-I SDR25 Mode

Table 5-74 and Table 5-75 present Timing requirements and Switching characteristics for MMCi - SDR25

in receiver and transmitter mode (see Figure 5-76 and Figure 5-77).

Table 5-74. Timing Requirements for MMCi - SDR25 Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SDR253

tsu(cmdV-clkH)

Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge

2.15

SDR254

th(clkH-cmdV)

Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge

1.67

SDR257

tsu(dV-clkH)

Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock

edge

2.15

SDR258

th(clkH-dV)

Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge

1.67

(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).

Table 5-75. Switching Characteristics for MMCi - SDR25 Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SDR251

fop(clk)

Operating frequency, MMCi_CLK

MHz

SDR252H

tw(clkH)

Pulse duration, MMCi_CLK high

9.2

SDR252L

tw(clkL)

Pulse duration, MMCi_CLK low

9.2

SDR255

td(clkL-cmdV)

Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition

-6.1

3.1

SDR256

td(clkL-dV)

Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]

transition

-6.1

3.1

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