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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 207 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 207 Page - Texas Instruments |
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207 / 277 page  207 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated 5.9.5.16 eMMC/SD/SDIO NOTE The I/O Timings provided in this section are valid only when the corresponding DLL Delays are configured for some MMC usage modes, as described in Table 5-80. NOTE The MMCi (i = 0 to 1) controller is also referred to as MMCi. For more details about features and additional description information on the device Multi Media Card, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.9.5.16.1 MMCi — eMMC/SD/SDIO Card Interface MMCi interface is compliant with the SD Standard v3.01 as well as JC64 eMMC standard v4.5 and it supports the following SD Card and eMMC applications: • Default speed • High speed • UHS-I SDR12 • UHS-I SDR25 • UHS-I SDR50 • UHS-I SDR104 / HS200 • UHS-I DDR50 NOTE For more information, see section Multimedia Card/Secure Digital () Interface in the device TRM. 5.9.5.16.1.1 Default speed Mode Table 5-68 and Table 5-69 present Timing requirements and Switching characteristics for MMCi - Default Speed in receiver and transmitter mode (see Figure 5-70 and Figure 5-71) Table 5-68. Timing Requirements for MMCi - Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DSSD5 tsu(cmdV-clkH) Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge 1.65 ns DSSD6 th(clkH-cmdV) Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge 19.17 ns DSSD7 tsu(dV-clkH) Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge 1.65 ns DSSD8 th(clkH-dV) Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge 19.17 ns (1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1). Table 5-69. Switching Characteristics for MMCi - Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DSSD0 fop(clk) Operating frequency, MMCi_CLK 25 MHz DSSD1 tw(clkH) Pulse duration, MMCi_CLK high 18.7 ns DSSD2 tw(clkL) Pulse duration, MMCi_CLK low 18.7 ns DSSD3 td(clkL-cmdV) Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition - 13.6 13.6 ns DSSD4 td(clkL-dV) Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0] transition - 13.6 13.6 ns |
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