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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 212 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 212 Page - Texas Instruments |
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212 / 277 page  212 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated 5.9.5.16.1.6 UHS-I SDR104 / HS200 Mode Table 5-77 presents Timing requirements and Switching characteristics for MMCi - SDR104 in receiver and transmitter mode (see and Figure 5-79) Table 5-77. Switching Characteristics for MMCi - SDR104 / HS200 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR1041 fop(clk) Operating frequency, MMCi_CLK 142.86 MHz SDR1042H tw(clkH) Pulse duration, MMCi_CLK high 3.02 ns SDR1042L tw(clkL) Pulse duration, MMCi_CLK low 3.02 ns SDR1045 td(clkH-cmdV) Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition 1.12 5.10 ns SDR1046 td(clkH-dV) Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0] transition 1.12 5.10 ns (1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1). Figure 5-79. eMMC/SD/SDIO in - High Speed SDR104 / HS200 - Transmitter Mode 5.9.5.16.1.7 UHS-I DDR50 Mode Table 5-78 and Table 5-79 present Timing requirements and Switching characteristics for MMCi - DDR50 in receiver and transmitter mode (see Figure 5-80 and Figure 5-81). Table 5-78. Timing Requirements for MMCi - DDR50 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR505 tsu(cmdV-clkH) Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge 8 ns DDR506 th(clkH-cmdV) Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge 1.91 ns DDR507 tsu(dV-clk) Setup time, MMCi_DAT[j:0] valid before MMCi_CLK transition 2.51 ns DDR508 th(clk-dV) Hold time, MMCi_DAT[j:0] valid after MMCi_CLK transition 1.67 ns (1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1). Table 5-79. Switching Characteristics for MMCi - DDR50 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR500 fop(clk) Operating frequency, MMCi_CLK 40 MHz DDR501 tw(clkH) Pulse duration, MMCi_CLK high 11.58 ns DDR502 tw(clkL) Pulse duration, MMCi_CLK low 11.58 ns DDR503 td(clk-cmdV) Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition 3.4 17.98 ns DDR504 td(clk-dV) Delay time, MMCi_CLK transition to MMCi_DAT[j:0] transition 2.9 8.79 ns |
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