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AM652X Fiches technique(PDF) 208 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 208 Page - Texas Instruments |
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208 / 277 page ![]() 208 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated (1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1). Figure 5-70. eMMC/SD/SDIO in - Default Speed - Receiver Mode Figure 5-71. eMMC/SD/SDIO in - Default Speed - Transmitter Mode 5.9.5.16.1.2 High speed Mode Table 5-70 and Table 5-71 present Timing requirements and Switching characteristics for MMCi - High Speed in receiver and transmitter mode (see Figure 5-72 and Figure 5-73). Table 5-70. Timing Requirements for MMCi - High Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT HSSD3 tsu(cmdV-clkH) Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge 2.15 ns HSSD4 th(clkH-cmdV) Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge 2.67 ns HSSD7 tsu(dV-clkH) Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge 2.15 ns HSSD8 th(clkH-dV) Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge 2.67 ns (1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1). Table 5-71. Switching Characteristics for MMCi - High Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT HSSD1 fop(clk) Operating frequency, MMCi_CLK 50 MHz HSSD2H tw(clkH) Pulse duration, MMCi_CLK high 11.58 ns HSSD2L tw(clkL) Pulse duration, MMCi_CLK low 11.58 ns HSSD5 td(clkL-cmdV) Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition -6.1 3.1 ns HSSD6 td(clkL-dV) Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0] transition -6.1 3.1 ns |
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