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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM186ED-20KC/W Fiches technique(PDF) 64 Page - Advanced Micro Devices |
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AM186ED-20KC/W Fiches technique(HTML) 64 Page - Advanced Micro Devices |
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64 / 88 page  64 Am186ED/EDLV Microcontrollers PRELI M INARY D RA F T SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Read Cycle (20 MHz and 25 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Parameter Preliminary Unit 20 MHz 25 MHz No. Symbol Description Min Max Min Max General Timing Requirements 1tDVCL Data in Setup 10 10 ns 2tCLDX Data in Hold(c) 33 ns General Timing Responses 3tCHSV Status Active Delay 0 25 0 20 ns 4tCLSH Status Inactive Delay 0 25 0 20 ns 5tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 6tCLAX Address Hold 0 25 0 20 ns 8tCHDX Status Hold Time 0 0 ns 9tCHLH ALE Active Delay 25 20 ns 10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns 11 tCHLL ALE Inactive Delay 25 20 ns 12 tAVLL AD Address Valid to ALE Low(a) tCLCH –2 tCLCH–2 ns 13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL–2 tCHCL–2 ns 14 tAVCH AD Address Valid to Clock High 0 0 ns 15 tCLAZ AD Address Float Delay tCLAX=0 25 tCLAX=0 20 ns 16 tCLCSV MCS/PCS Active Delay 0 25 0 20 ns 17 tCXCSX MCS/PCS Hold from Command Inactive(a) tCLCH–2 tCLCH–2 ns 18 tCHCSX MCS/PCS Inactive Delay 0 25 0 20 ns 19 tDXDL DEN Inactive to DT/R Low(a) 00 ns 20 tCVCTV Control Active Delay 1(b) 025 0 20 ns 21 tCVDEX DEN Inactive Delay 0 25 0 20 ns 22 tCHCTV Control Active Delay 2(b) 025 0 20 ns 23 tLHAV ALE High to Address Valid 20 15 ns 99 tPLAL PCS Active to ALE Inactive 15 28 15 24 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 0 ns 25 tCLRL RD Active Delay 0 25 0 20 ns 26 tRLRH RD Pulse Width 2tCLCL–15=85 2tCLCL–15=65 ns 27 tCLRH RD Inactive Delay 0 25 0 20 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns 29 tRHAV RD Inactive to AD Address Active(a) tCLCL–10=40 tCLCL–10=30 ns 41 tDSHLH DS Inactive to ALE Active tCLCH–2=21 tCLCH–2=16 ns 59 tRHDX RD High to Data Hold on AD Bus(c) 00 ns 66 tAVRL A Address Valid to RD Low(a) tCLCL+ tCHCL–3 tCLCL+ tCHCL–3 ns 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 25 0 20 ns 68 tCHAV CLKOUTA High to A Address Valid 0 25 0 20 ns |
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