STV9937 datasheet(29/49 Pages) STMICROELECTRONICS

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STV9937

Pixel Clock Generator

The Pixel Clock Generator is used to synchronize the display clock with the horizontal

synchronisation (Hsync) signal. This generator is based on a PLL function used to perform correct

jitter. The pixel frequency is defined with the horizontal line frequency and the horizontal resolution.

Pixel Frequency (FPIXEL2) = 12 x HR[6:0] x fHLINE

The VCO[1:0] value is used to select the appropriate curve partition of the VCO.

The PLL generates:

●

a pixel clock for the OSD from 7.68 MHz to 120 MHz: FPIXEL2

●

a pixel clock for the PictureBooSTTM (PB) from 30 to 60 MHz: FPIXEL1.

The PictureBooSTTM pixel clock provides the resolution of the PB pixel.It is locked on the HSYNC

signal and the referenced edge is programmed using the HSP bit.

When the monitor resolution is changing, the micro controller changes the OSD horizontal

resolution to adapt the width of the OSD window. In this case, the frequency of the PB clock is

changing also. So the width and the position and the resolution of the PB window is changing.

Table 33: VCO Curve Partition

VCO Value (Binary)

VCO Curve Partition

7.68 MHz < FPIXEL2 < 15 MHz (Default Value)

MHz < FPIXEL2 < 30 MHz

MHz < FPIXEL2 < 60 MHz

MHz < FPIXEL2 < 120 MHz

Table 34: VCO Range

FWR

FAC

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80h

00h

VCO[1:0]

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