PIC18C Reference Manual

DS39504A-page 4-6

 2000 Microchip Technology Inc.

4.3

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). Fetch takes one instruction

cycle, while decode and execute takes another instruction cycle. However, due to pipelining, each

instruction effectively executes in one cycle. If an instruction causes the program counter to

change (e.g. GOTO instruction), then an extra cycle is required to complete the instruction (See

Example 4-1).

The instruction fetch begins with the program counter incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in

cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data

memory is read during Q2 (operand read) and written during Q4 (destination write).

Example 4-1 shows the operation of the two stage pipeline for the instruction sequence shown.

the third instruction (CALL SUB_1) is executed. When the third instruction completes execution,

the CPU forces the address of instruction four onto the Stack and then changes the Program

Counter (PC) to the address of SUB_1. This means that the instruction that was fetched during

executed and the instruction at address SUB_1 + 2 is fetched.

Example 4-1: Instruction Pipeline Flow

Most instructions are single cycle. Program branches take two cycles, since the fetch instruction is “flushed” from

the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF

PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

Fetch SUB_1 +2