PIC18C Reference Manual

DS39504A-page 4-4

 2000 Microchip Technology Inc.

Figure 4-2:

General Enhanced MCU Block Diagram

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKIN

OSC2/CLKOUT

MCLR

PORTA

PORTB

PORTC

RA4

RA5

RB0/INT0

RB<7:4>

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

Brown-out

Reset

Note 1: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are

device dependent.

RA3

RA2

RA1

RA0

Timing

Generation

4X PLL

RB1/INT1

Data Latch

Data RAM

(upto4K

address reach)

Address Latch

Address<12>

12

Bank0, F

BSR

FSR0

FSR1

FSR2

inc / dec

logic

Decode

412

4

PCH

PCL

PCLATH

8

31 Level Stack

Program Counter

PRODL

PRODH

8x 8Multiply

W

8

BITOP

8

8

ALU<8>

8

Address Latch

Program Memory

(up to 2M Bytes)

Data Latch

20

21

21

16

8

8

8

Table Pointer<21>

inc/dec logic

21

8

Data Bus<8>

TABLELATCH

8

Instruction

12

3

ROMLATCH

PORTD

RB2/INT2

RB3

T1OSI

T1OSO

PCLATU

PCU

RA6

Precision

Reference

Bandgap

Register

8

Addressable

CCP’s

Synchronous

Timer0

Timer1

Timer2

Serial Port

A/D Converter

Timer3

Enhanced

USART

Master

Other

Peripherals

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

PORTE

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

Peripheral Modules (Note 1)

CAN

USB

PORTx

Rx0

Rx1

Rx2

Rx3

Rx4

Rx5

Rx6

Rx7

CCP’s