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SLG46110V Fiches technique(PDF) 23 Page - Dialog Semiconductor |
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SLG46110V Fiches technique(HTML) 23 Page - Dialog Semiconductor |
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23 / 82 page ![]() 000-0046110-106 Page 22 of 81 SLG46110 7.7 Register OE IO Structure 7.7.1 Register OE IO Structure (for Pins 3, 4, 8, 9, 12) Figure 4. Register OE IO Structure Diagram PAD Digital In S0 S1 pull_up_en 10 k 90 k 900 k Res_sel[1:0] 00: floating 01: 10 k 10: 100 k 11: 1 M wosmt_en smt_en lv_en Low Voltage Input Schmitt Trigger Input Non-Schmitt Trigger Input Mode [2:0] 000: Digital In without Schmitt Trigger, wosmt_en=1 001: Digital In with Schmitt Trigger, smt_en=1 010: Low Voltage Digital In mode, lv_en = 1 011: analog IO mode 100: push-pull mode, pp_en=1 101: NMOS open drain mode, odn_en=1 110: PMOS open drain mode, odp_en=1 111: analog IO and NMOS open-drain mode, odn_en=1 and AIO_en=1 Analog IO Digital Out Digital Out OE odn_en OE odn_en Digital Out OE 2x_en pp_en 2x_en odp_en Digital Out OE pp_en 2x_en odp_en |
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