80960 datasheet(4/77 Pages) INTEL

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80960JA/JF/JD/JT 3.3 V Microprocessor

Advance Information Datasheet

Figures

80960Jx Microprocessor Package Options...........................................................7

80960Jx Block Diagram ........................................................................................9

132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22

132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23

132-Lead PQFP - Top View ................................................................................26

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up ..................29

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30

VCC5 Current-Limiting Resistor ..........................................................................40

VCCPLL Lowpass Filter ......................................................................................41

AC Test Load ......................................................................................................47

Output Delay or Hold vs. Load Capacitance .......................................................48

TLX vs. AD Bus Load Capacitance......................................................................48

80960JA/JF ICC Active (Power Supply) vs. Frequency .......................................49

80960JA/JF ICC Active (Thermal) vs. Frequency ................................................49

80960JD ICC Active (Power Supply) vs. Frequency............................................50

80960JD ICC Active (Thermal) vs. Frequency.....................................................50

80960JT ICC Active (Power Supply) vs. Frequency ...........................................51

80960JT ICC Active (Thermal) vs. Frequency .....................................................51

CLKIN Waveform ................................................................................................52

TOV1 Output Delay Waveform .............................................................................52

TOF Output Float Waveform................................................................................53

TIS1 and TIH1 Input Setup and Hold Waveform...................................................53

TIS2 and TIH2 Input Setup and Hold Waveform...................................................53

TIS3 and TIH3 Input Setup and Hold Waveform...................................................54

TIS4 and TIH4 Input Setup and Hold Waveform...................................................54

TLX, TLXL and TLXA Relative Timings Waveform.................................................55

DT/R and DEN Timings Waveform .....................................................................55

TCK Waveform....................................................................................................56

TBSIS1 and TBSIH1 Input Setup and Hold Waveforms .........................................56

TBSOV1 and TBSOF1 Output Delay and Output Float Waveform..........................56

TBSOV2 and TBSOF2 Output Delay and Output Float Waveform..........................57

TBSIS2 and TBSIH2 Input Setup and Hold Waveform ...........................................57

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58

Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................59

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................61

Burst Read and Write Transactions With 1, 0 Wait States and

Extra Tr State on Read, 16-Bit Bus .....................................................................62

Double Word Read Bus Request, Misaligned One Byte From

Quad Word Boundary, 32-Bit Bus, Little Endian .................................................63

HOLD/HOLDA Waveform For Bus Arbitration ....................................................64

Cold Reset Waveform .........................................................................................65

Warm Reset Waveform .......................................................................................66

Entering the ONCE State ....................................................................................67

Bus States with Arbitration ..................................................................................68

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73

80960JT Device Identification Register...............................................................74

80960JD Device Identification Register ..............................................................75

80960JA/JF Device Identification Register .........................................................76

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