WM8232 datasheet(32/141 Pages) CIRRUS

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WM8232

Rev 4.6

CMOS OUTPUT MODE

IN1

IN2

IN3

MCLK x1

MCLK x3 (OCLK)

OP9

OP8

OP7

OP6

OP5

OP4

IN1

IN2

IN3

OP3

OP2

OP1

OP0

MCLK x3 (OC1)

IN1

IN2

MCLK x1

(ADCLK)

ADC1

ADC2

IN3

ADC3

OP9

IN1[9]

IN2[9]

IN3[9]

OP8

IN1[8]

IN2[8]

IN3[8]

OP7

IN1[7]

IN2[7]

IN3[7]

OP6

IN1[6]

IN2[6]

IN3[6]

OP5

IN1[5]

IN2[5]

IN3[5]

OP4

IN1[4]

IN2[4]

IN3[4]

OP3

IN1[3]

IN2[3]

IN3[3]

OP2

IN1[2]

IN2[2]

IN3[2]

OP1

IN1[1]

IN2[1]

IN3[1]

OP0

IN1[0]

IN2[0]

IN3[0]

Table 12 10-bit CMOS Output Format

CLOCK TIMING CONFIGURATION

The RSMP signal, VSMP signal and clock output from CLK pin are generated internally by 60 tap DLL

circuit. The rising and falling timing of each clock is set by DLL tap setting. The following setting and

timing chart shows example configuration for RSMP, VSMP and CLK1.

RSMP: 0x82(RSMP_RISE)=0x07(dec7), 0x83(RSMP_FALL)=0x10(dec16)

VSMP: 0x84(VSMP_RISE)=0x1C(dec28), 0x85(VSMP_FALL=0x29(dec41)

CLK1: 0x87(CLK1_RISE)=0x39(dec57), 0x88(CLK1_FALL)=0x0B(dec11)

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