PC87415VCG datasheet(17/42 Pages) NSC

17 / 42 page

60 Bus Master IDE Control and Status Registers

Offset from

Description

BAR4

CHANNEL 1 BUS MASTER IDE COMMAND REGISTER

Default value is 00h

Bit 0 StartStop Bus Master

0 Stop Bus Master transfers Master operation can be halted by writinga0to this bit All state

information is lost whena0is written

1 Start Bus Master transfers This enables bus master operation of the controller Bus master

operation begins when this bit is detected changing from zero to one The controller will transfer

data between the IDE device and memory only when this bit is set

Bit 1 – 2 Reserved

Bit 3 Read or Write Control

0 PCI bus master read

1 PCI bus master write

Bit 4 – 7 Reserved

RESERVED

CHANNEL 1 BUS MASTER IDE STATUS REGISTER

Writes to this register cause bit(s) to be reset Bits 1

and 2 are reset wherever the register is written with a ‘‘1’’ in the corresponding bit location Default value is

00h

Bit 0 Bus Master IDE Active This bit is set when the Start bit is written to the Bus Master IDE Command

region is set in the region descriptor It is also cleared when the Start bit is cleared in the Bus Master

IDE Command Register

Bit 1 Error This bit is set when the controller encounters an error in transferring data tofrom memory This

bit is cleared whena1is written to it by software

Bit 2 Interrupt This bit is set by the rising edge of CH1

INT This bit is cleared whena1is written to it by

software

Bit 3 – 4 Reserved

Bit 5 Drive 1 DMA Capable Bus Master IDE transfers to drive 1 on channel 1 are qualified by this bit

0 Drive 1 is not DMA capable

1 Drive 1 is DMA capable

Bit 6 Drive 2 DMA Capable Bus Master IDE transfers to drive 2 on channel 1 are qualified by this bit

0 Drive 2 is not DMA capable

1 Drive 2 is DMA capable

Bit 7 Simplex only This read-only bit is always 0 indicating that both channels can operate independently

and can be used at the same time

Reserved

04 – 07

CHANNEL 1 BUS MASTER IDE PRD TABLE ADDRESS

Default value is 00000000h

Bit 0 – 1 Reserved

Bit 2 – 31 Base address of channel 1 Descriptor table Corresponds to AD 312

CHANNEL 2 BUS MASTER IDE COMMAND REGISTER

Default value is 00h

Bit 0 StartStop Bus Master

0 Stop Bus Master transfers Master operation can be halted by writinga0to this bit All state

information is lost whena0is written

1 Start Bus Master transfers This enables bus master operation of the controller Bus master

operation begins when this bit is detected changing from zero to one The controller will transfer

data between the IDE device and memory only when this bit is set

Bit 1 – 2 Reserved

Bit 3 Read or Write Control

0 PCI bus master read

1 PCI bus master write

Bit 4 – 7 Reserved

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