7332 DMA

The DMA handshaking protocol is as follows

1 The device receives a command to start a DMA transfer

2 The IDE controller waits for DMARQ from the drive to be

asserted before issuing the data cycle

3 When DMARQ is asserted

the controller asserts

DMACK and begins to do data transfers until either there

is no more data to be transferred or DMARQ is de-as-

serted DMARQ is sampled on a cycle by cycle bases

4 When the last command is complete and DMARQ is de-

asserted the device de-asserts DMACK

TLF12497 – 10

734 Interrupt Routing

Channel 1 and 2 interrupts can be routed to either IRQ14 IRQ15 respectively or to INTA on the PCI bus in various combinations

Table II shows all the combinations of interrupt routing

TABLE II Interrupt Routing

CMD(0)

CTRL(6)

CTRL(8)

CTRL(9)

CTRL(4)

CTRL(5)

PIF(0)

PIF(2)

Enable

Mask

Mask

Mask

Route

Route

Native

Native

INTA

IRQ14

IRQ15

Notes

INTA

CH1

INTRQ

CH2

INTRQ

Opt 0

Opt 1

CH1

CH2

0x

x

x

x

x

x

x

x

x

x

1

1

0

0

0

0

0

0

0

x

CH1

INTRQ

CH2

INTRQ

2

1

0

0

1

0

0

0

0

x

CH1

INTRQ

x

2

1

0

1

0

0

0

0

0

x

x

CH2

INTRQ

2

10

1

1

0

0

0

1

x

x

x

2

1

0

0

0

1

0

0

0

(CH1

INTRQ)

x

CH2

INTRQ

2

1

0

0

0

0

1

0

0

(CH2

INTRQ)

CH1

INTRQ

x

2

1

0

0

0

1

1

0

0

(CH1

INTRQ

x

x

2

a

CH2

INTRQ)

1

0

0

0

x

x

1

1

(CH1

INTRQ

x

x

3

a

CH2

INTRQ)

1

0

0

1

x

x

1

1

(CH1

INTRQ)

x

x

3

1

0

1

0

x

x

1

1

(CH2

INTRQ)

x

x

3

10

1

1

x

x

1

1

x

x

x

3

11

x

x

x

x

1

1

x

x

x

3

Note 1

Device is disabled

Note 2

Device responds to Channel 1 to 1Fx and 3F6 Channel 2 to 17x and 376

Note 3

Device responds to Channel 1 to BAR0 and BAR1 Channel 2 to BAR2 and BAR3

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