CS8406-CSZ datasheet(24/39 Pages) CIRRUS

24 / 39 page

DS580F6

CS8406

Note: There are separate complete buffers for the Channel Status and User bits. This control bit deter-

mines which buffer appears in the address space.

EFTCI - E to F C-data buffer transfer inhibit bit.

Default = ‘0’

0 - Allow C-data E to F buffer transfers

1 - Inhibit C-data E to F buffer transfers

CAM - C-data buffer control port access mode bit

Default = ‘0’

0 - One-Byte Mode

1 - Two-Byte Mode

8.14 User Data Buffer Control (13h)

UD - User bit data source specifier

Default = ‘0’

0 - U Pin is the source of transmitted U data

1 - U data buffer is the source of transmitted U data

UBM1:0 - Sets the operating mode of the AES3 User bit manager

Default = ‘00’

00 - Transmit all zeros mode

01 - Block Mode

10 - Reserved

11 - Reserved

EFTUI - E to F U-data buffer transfer inhibit bit (valid in Block Mode only).

Default = ‘0’

0 - Allow U-data E to F buffer transfers

1 - Inhibit U-data E to F buffer transfers

8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h)

Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to

Block Mode) is accessible through these register addresses.

8.16 CS8406 I.D. and Version Register (7Fh) (Read Only)

ID[3:0] - ID code for the CS8406. Permanently set to 1110

VER[3:0] = 0001 (revision A)

VER[3:0] = 0010 (revision B)

432

UBM1

UBM0

EFTUI

432

ID3

ID2

ID1

ID0

VER3

VER2

VER1

VER0

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