CS8406-CSZ datasheet(19/39 Pages) CIRRUS

19 / 39 page

DS580F6

CS8406

8. CONTROL PORT REGISTER BIT DEFINITIONS

8.1

Memory Address Pointer (MAP)

Not a register

MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.

8.2

Default = ‘000000’

Control 1 (01h)

VSET - Transmitted Validity bit level

Default = ‘0’

0 - Indicates data is valid, linear PCM audio data

1 - Indicates data is invalid or not linear PCM audio data

MUTEAES - Mute control for the AES transmitter output

Default = ‘0’

0 - Not Muted

1 - Muted

INT1:0 - Interrupt output pin (INT) control

Default = ‘00’

00 - Active high; high output indicates interrupt condition has occurred

01 - Active low, low output indicates an interrupt condition has occurred

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.

11 - Reserved

TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier

Default = ‘0’

0 - TCBL is an input

1 - TCBL is an output

8.3

Control 2 (02h)

MMT - Select AES3 transmitter mono or stereo operation

Default = ‘0’

0 - Normal stereo operation

1 - Output either left or right channel inputs into consecutive subframe outputs (Mono Mode, left or right is

determined by MMTLR bit)

432

MAP6

MAP5

MAP4

MAP3

MAP2

MAP1

MAP0

VSET

MUTEAES

INT1

INT0

TCBLD

MMT

MMTCS

MMTLR

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