STM32F745ZE datasheet(40/227 Pages) STMICROELECTRONICS

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Functional overview

STM32F745xx STM32F746xx

40/227

DocID027590 Rev 4

2.29

Audio and LCD PLL(PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the

PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the LCD-TFT clock.

2.30

SD/SDIO/MMC card host interface (SDMMC)

An SDMMC host interface is available, that supports MultiMediaCard System Specification

Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory

card specification version 2.0.

The SDMMC card specification version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a

stack of MMC4.1 or previous.

The SDMMC can be served by the DMA controller

2.31

Ethernet MAC interface with dedicated DMA and IEEE 1588

support

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for

ethernet LAN communications through an industry-standard medium-independent interface

(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an

external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,

fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals

for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.

The devices include the following features:

•

Support of 10 and 100 Mbit/s rates

•

Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors

•

Tagged MAC frame support (VLAN support)

•

Half-duplex (CSMA/CD) and full-duplex operation

•

MAC control sublayer (control frames) support

•

32-bit CRC generation and removal

•

Several address filtering modes for physical and multicast address (multicast and

group addresses)

•

32-bit status code for each transmitted or received frame

•

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the

receive FIFO are both 2 Kbytes.

•

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008

(PTP V2) with the time stamp comparator connected to the TIM2 input

•

Triggers interrupt when system time becomes greater than target time

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