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TMS320VC5502 Fiches technique(PDF) 137 Page - Texas Instruments |
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TMS320VC5502 Fiches technique(HTML) 137 Page - Texas Instruments |
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137 / 189 page ![]() www.ti.com Setup = 2 Strobe = 3 Not Ready Hold = 2 BE Address Read Data A2 A1 A2 A1 A2 A1 A2 A1 A5 A4 A3 EMIF.ARDY A7 A7 A6 A6 A5 ECLKOUT1 EMIF.CEx EMIF.A[21:2] EMIF.D[31:0] EMIF.AOE/SOE/SDRAS (see Note A) EMIF.ARE/SADS/SDCAS/SRE (see Note A) EMIF.BE[3:0] EMIF.AWE/SWE/SDWE (see Note A) A. EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals), EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses. TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Figure 5-8. Asynchronous Memory Read Timings Specifications 137 |
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