EMC2103 datasheet(69/85 Pages) MICROCHIP

69 / 85 page

RPM-Based Fan Controller with Hardware Thermal Shutdown

Datasheet

 2013 Microchip Technology Inc.

DS0005250A-page 69

The GPIO Input Register indicates the state of the corresponding GPIO pin. When a GPIO is

configured as an input, any change of state will assert the ALERT pin (unless GPIO interrupts are

masked, see Section 6.15).

Bit 1 - GPIO2_IN - Indicates the pin state of the GPIO2 pin regardless of the pin functionality.

Bit 0 - GPIO1_IN - Indicates the pin state of the GPIO1 pin regardless of the pin functionality.

6.37

GPIO Output Register (EMC2103-2 and EMC2103-4 Only)

The GPIO Output Register controls the state of the corresponding pins when they are configured as

outputs.

If the output is configured as an open-drain output, then it requires a pull-up resistor to VDD. Setting

the corresponding bit to a ‘1’ will act to disable the output allowing the pull-up resistor to pull the output

high. Setting the corresponding bit to a ‘0’ will enable the output and drive the pin to a logical ‘0’ state.

If the output is configured as a push-pull output, then output pin will immediately be driven to match

the corresponding bit setting.

Bit 1 - GPIO2_OUT - Controls the pin state of the GPIO2 pin when it is configured as a GPIO output.

Bit 0 - GPIO1_OUT - Controls the pin state of the GPIO1 pin when it is configured as a GPIO output.

6.38

GPIO Interrupt Enable Register (EMC2103-2 and EMC2103-4

Only)

The GPIO Interrupt Enable Register enables the GPIOs to assert the ALERT pin when they change

state. When the GPIO pins are configured as outputs, then these bits are ignored.

Bit 1 - GPIO2_INT_EN - Allows the ALERT pin to be asserted when the GPIO2 pin changes state

(when configured as an input).



‘0’ (default) - The ALERT pin will not be asserted when the GPIO2 pin changes state (when

configured as an input).



‘1’ - The ALERT pin will be asserted when the GPIO2 pin changes state (when configured as an

input)

Bit 0 - GPIO1_INT_EN - Allows the ALERT pin to be asserted when the GPIO1 pin changes state

(when configured as an input).

Table 6.54 GPIO Output Register

ADDR

R/W

DEFAULT

E4h

R/W

GPIO

Output 1

GPIO2

_OUT

GPIO1

_OUT

00h

Table 6.55 GPIO Interrupt Enable Register

ADDR

R/W

DEFAULT

E5h

R/W

GPIO

Interrupt

Enable

GPIO2_

INT_EN

GPIO1_

INT_EN

00h

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