EMC2103 datasheet(50/85 Pages) MICROCHIP

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RPM-Based Fan Controller with Hardware Thermal Shutdown

Datasheet

DS0005250A-page 50

 2013 Microchip Technology Inc.

6.10

Configuration Register

The Configuration Register controls the basic functionality of the EMC2103. The bits are described

below.

Bit 7 - MASK - Blocks the ALERT pin from being asserted.



‘0’ (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin

will be asserted (unless individually masked via the Mask Register)



‘1’ - The ALERT pin is masked and will not be asserted.

Bit 3 - SYS3 (EMC2103-2 and EMC2103-4 only) - Enables the high temperature limit for the External

Diode 3 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.1).



‘0’ (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the

temperature meets or exceeds the limit, the ALERT pin will be asserted normally.



‘1’ - the External Diode 3 channel high limit will be linked to the SYS_SHDN pin. If the temperature

meets or exceeds the limit then the SYS_SHDN pin will be asserted. The SYS_SHDN pin will be

released when the temperature drops below the high limit. The ALERT pin will be asserted

normally.

Bit 2 - SYS2 (EMC2103-2 and EMC2103-4 only) - Enables the high temperature limit for the External

Diode 2 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.1).



‘0’ (default) - the External Diode 2 channel high limit will not be linked to the SYS_SHDN pin. If the

temperature meets or exceeds the limit, the ALERT pin will be asserted normally.



‘1’ - the External Diode 2 channel high limit will be linked to the SYS_SHDN pin. If the temperature

meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be

asserted normally.

Bit 1 - SYS1 - Enables the high temperature limit for the External Diode 1 channel to trigger the Critical

/ Thermal Shutdown circuitry (see Section 5.1).



‘0’ (default) - The External Diode 1 channel high limit will not be linked to the SYS_SHDN pin. If

the temperature meets or exceeds the limit, the ALERT pin will be asserted normally.



‘1’ - The External Diode 1 channel high limit will be linked to the SYS_SHDN pin. If the temperature

meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be

asserted normally.

Bit 0 - APD (EMC2103-2 and EMC2103-4 only) - This bit enables the Anti-parallel diode functionality

on the External Diode 3 pins (DP3 and DN3).



‘0’ (default) - The Anti-parallel diode functionality is disabled. The External Diode 2 channel can be

configured for any type of diode



‘1’ - The Anti-parallel diode functionality is enabled. Both the External Diode 2 and 3 channels are

configured to support a diode or diode connected transistor (such as a 2N3904).

APPLICATION NOTE: When the APD diode is enabled, there will be a delay of a full temperature update before

any comparisons and functionality associated with the External Diode 3 channel will be

implemented. This includes the SYS3 bit operation, limit comparisons, and look up table

comparisons.

The Configuration Register is software locked.

Table 6.15 Configuration Register

ADDR

R/W

DEFAULT

20h

R/W

Configuration

MASK

SYS3

SYS2

SYS1

APD

00h

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