EMC2103 datasheet(61/85 Pages) MICROCHIP

61 / 85 page

RPM-Based Fan Controller with Hardware Thermal Shutdown

Datasheet

 2013 Microchip Technology Inc.

DS0005250A-page 61

The Gain Register stores the gain terms used by the proportional and integral portions of the RPM

based Fan Speed Control Algorithm. These terms will affect the FSC closed loop acquisition,

overshoot, and settling as would be expected in a classic PID system.

6.25

Fan Spin Up Configuration Register

The Fan Spin Up Configuration Register controls the settings of Spin Up Routine.

Bit 7 - 6 - DRIVE_FAIL_CNT[1:0] - Determines how many update cycles are used for the Drive Fail

detection function as shown in Table 6.40. This circuitry determines whether the fan can be driven to

the desired tach target.

Bit 5 - NOKICK - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the

programmed spin up time before driving it at the programmed level.



‘0’ (default) - The Spin Up Routine will drive the PWM to 100% for 1/4 of the programmed spin up

time before reverting to the programmed spin level.

Table 6.38 Gain Decode

GAIND OR GAINP OR GAINI [1:0]

RESPECTIVE GAIN FACTOR

4x (default)

Table 6.39 Fan Spin Up Configuration Register

ADDR

R/W

DEFAULT

46h

R/W

Fan Spin Up

Configuration

DRIVE_FAIL

_CNT [1:0]

NOK

ICK

SPIN_LVL[2:0]

SPINUP_TIME

[1:0]

19h

Table 6.40 DRIVE_FAIL_CNT[1:0] Bit Decode

DRIVE_FAIL_CNT[1:0]

NUMBER OF UPDATE PERIODS

Disabled - the Drive Fail detection circuitry is

disabled

16 - the Drive Fail detection circuitry will count for 16

update periods

32 - the Drive Fail detection circuitry will count for 32

update periods

64 - the Drive Fail detection circuitry will count for 64

update periods

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