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CS5530 Fiches technique(PDF) 235 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce CS5530
Description  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5530 Fiches technique(HTML) 235 Page - National Semiconductor (TI)

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Revision 4.1
235
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Electrical Specifications (Continued)
Figure 5-6. Display TFT/TV Outputs Delays
Table 5-15. Video Interface: Setup/Hold and Delay Times
Symbol
Parameter
Min
Typ
Max
Units
Comments
Setup/Hold Times
tDisplaySetup
Display setup to rising PCLK:
VSYNC, HSYNC, FP_DISP_ENA,
FP_VSYNC, FP_HSYNC, PIXEL[23:0]
3.0
ns
All setup/hold
times are
derived as
shown in
Figure 5-2.
tDisplayHold
Display hold from rising PCLK:
VSYNC, HSYNC, FP_DISP_ENA,
FP_VSYNC, FP_HSYNC, PIXEL[23:0]
0
tVID_VALSetup
VID_VAL setup to rising VID_CLK
3.75
ns
tVID_VALHold
VID_VAL hold from rising VID_CLK
0
ns
tVID_DATASetup
VID_DATA setup to rising VID_CLK
3.75
ns
Also applies to
PIXEL[23;16]
when in 16-bit
video mode.
tVID_DATAHold
VID_DATA hold from rising VID_CLK
0
ns
Delay Times
FPOUTMinDelay,
FPOUTMaxDelay
TFT/TV output delays from FP_CLK:
FP_DATA[17:0], FP_HSYNC_OUT,
FP_VSYNC_OUT,
FP_DISP_ENA_OUT, FP_ENA_VDD,
FP_ENA_BKL, FP_CLK_EVEN
0.1
5.2
ns
All flat panel
applications use
the falling edge
of FP_CLK to
latch their data.
VID_RDYMinDelayE,
VID_RDYMaxDelayE
VID_RDY delay from falling VID_CLK
(early mode)
3
10.5
ns
The mode for
VID_RDY (early
or normal) is set
with "Video Con-
figuration Regis-
ter"
VID_RDYMinDelayN,
VID_RDYMaxDelayN
VID_RDY delay from rising VID_CLK
(normal mode)
39.5
ns
FP_CLK
FPOUTMinDelay
FPOUTMaxDelay
TFT/TV Outputs



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