CS5530 datasheet(50/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

3.3.3

DOT Clock

The DOT clock (DCLK) is generated from the 14.31818

MHz input (CLK_14MHZ). A combination of a phase

locked loop (PLL), linear feedback shift register (LFSR)

and divisors are used to generate the desired frequencies

for the DOT clock. The divisors and LFSR are config-

urable through the F4BAR+Memory Offset 24h. The mini-

mum frequency of DCLK is 10 MHz and the maximum is

200 MHz.

DCLK provides a video clock for the GXLV processor. For

applications that do not use the GXLV processor’s video,

this is an available clock for general purpose use.

The system clock distribution for a CS5530/GXLV proces-

sor based system is shown in Figure 3-6.

Figure 3-6. System Clock Distribution

DCLKto GXLVProcessor

DCLK

PLL

÷N

TVCLK from TV Controller

Clock

Geode™ CS5530

48 MHz Clock to USB of CS5530

PCICLK to GXLV Processor

PCICLK

PCICLK to PCI Related Device

PCICLK to PCI Bus

Geode™

SDRAMCLK to SDRAM

14 MHz Clock to Super I/O

14.318 MHz

Crystal

32 KHz for Reset and

Power Management

14 MHz Clock to TV Controller

ISACLK to ISA Bus

SUSP_3V

OE#

from CS5530

24.576 MHz Clock to AC97 Codec

GXLV

Generator

14 MHz Clock

I/O Companion

Processor

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