CS5530 datasheet(231/241 Pages) NSC

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Electrical Specifications (Continued)

Notes: 1. Worst case duty cycle.

2. Duty cycle is a function of PLL post divider.

3. Programmable to standard video frequencies.

4. Typical jitter < 650 ps peak-to-peak.

5. CLK_14MHZ input jitter < 500 ps peak-to-peak.

6. CLK_32K jitter = period of CLK_14MHZ

7. CLK_32K output frequency = CLK_14MHZ/436.95621.

8. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met

across the minimum peak-to-peak portion of the clock waveform as shown in Figure 5-3.

Figure 5-3. 3.3V PCICLK Waveform

Table 5-9. Clock Characteristics

Symbol

Parameter

Min

Max

Duty

Cycle

Unit

Comments

Output Signals

tf,tLcyc,tHcyc

DCLK Frequency

157.5

30/70

MHz

Notes 1 through 5

tLcyc,tHcyc

CLK_32K Frequency

32.768

50/50

kHz

Notes 6 and 7

tLcyc,tHcyc

CLK_14MHZ Frequency

14.31818

45/55

MHz

Input Signal

tcyc

PCICLK Cycle Time

∞

tHIGH

PCICLK High Time

tLOW

PCICLK Low Time

PCICLK Slew Time

V/ns

Note 8

0.3 VCC

0.4 VCC

0.5 VCC

tHIGH

0.6 VCC

tLOW

0.2 VCC

tcyc

0.4 VCC, peak-to-peak

(minimum)

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