VD5377 datasheet(79/88 Pages) STMICROELECTRONICS

79 / 88 page

Doc ID 022952 Rev 2

79/88

VD5377

I2C register map

CONTROL

dmib_ctrl_mode

DMIB controller timing switch

mode

0 = Manual (chosen by

dmib_timing reg)

1 = Automatic (system auto sets

the dmib_timing mode, status

reported in dmib_timing reg)

dmib_timing

PRW

DMIB controller timing mode

0 = Normal DMIB timing (same

as 376 with double expo time

possible)

1 = Sunlight DMIB timing

Reserved

PRW

Reserved

CDSOUT_SEL

cds_out_sel

1:0

PRW

Selects what is output from the

DMIB controller (going to

motion engine and or video

output data).

0 = CDS frame

2 = exposed frame

3 = black frame

Reserved

PRW

Reserved

FRAMEDUMP_

PIXDATA

framedump_pixdata

7:0

Pixel data in frame dump mode,

automatically incremented to

next pixel after a read of this

FRAMEDUMP_CTRL

framedump_en

PRW

Frame dump mode enable

0 = Disable

1 = Enable

framedump_start

Frame dump started

framedump_ready

Flag set when a frame is ready

to be read by host, Pixel[0] is

ready in register

FRAMEDUMP_PIXDATA.

framedump_done

Flag set when a complete frame

(400 pixels) has been read.

pci_test_enable

PRW

Muxed PCI data onto pads (2

bits nibble + FST + Qclk)

0 = Disable

1 = Enable

framedump_mire

PRW

In frame dump mode outputs a

grey scale image

(pixel_counter).

Table 38. I2C register map (continued)

Addr

(Hex)

SIgnal name

Bit

Type

Default

(Hex)

Comment

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