STCOM05 datasheet(21/58 Pages) STMICROELECTRONICS

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STCOM

Description

1.6.3

Embedded SRAM

The STCOM device has 128 kB of a static RAM. The Cortex™-M4 can perform byte, half

word (16 bits) or full word (32 bits) access to the SRAM at maximum speed, with zero wait

states for both read and write operations. The SRAM start address is 0x20000000, the end

address is 0x20001FFFF.

The SRAM is split into two blocks of 64 kB with a capability for concurrent access by AHB

master sub-systems.

The Cortex™-M4 can also execute a code from the RAM at a zero wait state.

1.6.4

Flexible static memory controller (FSMC)

The STCOM embeds a FSMC peripheral able to interface external memory devices. The

types of memory supported are:



Asynchronous parallel NOR Flash with up to 21-bit address bus (no synchronous

parallel NOR supported)



Asynchronous SRAM memories

The data bus can be selected between 16 bits or 8 bits (reducing the total amount of

accessible memory), for little or big endian operation.

The FSMC peripheral can connect up to 2 memories with 2 independent chip select lines

(Ebar). The maximum size of each memory is 4 MB. Having 2 chip select lines, the

maximum external memory size is 8 MB.

STCOM05 Fiches technique(PDF) 21 Page - STMicroelectronics