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LAN9730 Fiches technique(PDF) 24 Page - Microchip Technology |
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LAN9730 Fiches technique(HTML) 24 Page - Microchip Technology |
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24 / 222 page ![]() LAN9730/LAN9730i DS00001946A-page 24 2012-2015 Microchip Technology Inc. TABLE 2-7: POWER PINS AND GROUND PAD Num Pins Name Symbol Buffer Type Description 5 +3.3 V I/O Power VDD33IO P Refer to Chapter 3.0, "Power Connections" and the device reference schematics for connection information. 3 +3.3 V Ana- log Power VDD33A P Refer to Chapter 3.0, "Power Connections" and the device reference schematics for connection information. 2 +1.2 V Digital Core Power VDD12CORE P Refer to Chapter 3.0, "Power Connections" and the device reference schematics for connection information. 1 +1.2 V USB PLL Power VDD12USBPLL P This pin must be connected to VDD12CORE for proper operation. Refer to Chapter 3.0, "Power Connections" and the device reference schematics for additional connection information. 1 +1.2 V HSIC Power VDD12A P This pin must be connected to VDD12CORE for proper operation. Refer to Chapter 3.0, "Power Connections" and the device reference schematics for connection information. 1 +1.2 V Ether- net PLL Power VDD12PLL P This pin must be connected to VDD12CORE for proper operation. Refer to Chapter 3.0, "Power Connections" and the device reference schematics for additional connection information. Exposed pad on package bottom (Figure 2-1) Ground VSS P Common Ground |
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