XC164CS datasheet(30/71 Pages) INFINEON

30 / 71 page

XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

3.6

Capture/Compare Units (CAPCOM1/2)

The CAPCOM units support generation and control of timing sequences on up to

32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered

mode). The CAPCOM units are typically used to handle high speed I/O tasks such as

pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)

conversion, software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time

bases for each capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal

system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows

precise adjustments to the application specific requirements. In addition, external count

inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare

registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/

compare registers, each of which may be individually allocated to either CAPCOM timer

T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.

12 registers of the CAPCOM2 module have each one port pin associated with it which

serves as an input pin for triggering the capture function, or as an output pin to indicate

the occurrence of a compare event.

Table 6

Compare Modes (CAPCOM1/2)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3

Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;

only one compare event per timer period is generated

Double Register

Mode

Two registers operate on one pin;

pin toggles on each compare match;

several compare events per timer period are possible

Single Event Mode

Generates single edges or pulses;

can be used with any compare mode

XC164CS Fiches technique(PDF) 30 Page - Infineon Technologies AG

XC164CS Fiches technique(HTML) 30 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Fiches technique Télécharger

Lien URL