XC164CS datasheet(22/71 Pages) INFINEON

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XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

3.3

Central Processing Unit (CPU)

The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage

instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply

and accumulate unit (MAC), a register-file providing three register banks, and dedicated

SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel

shifter.

Figure 4

CPU Block Diagram

Based on these hardware provisions, most of the XC164’s instructions can be executed

in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift

and rotate instructions are always processed during one machine cycle independent of

the number of bits to be shifted. Also multiplication and most MAC instructions execute

in one single cycle. All multiple-cycle instructions have been optimized so that they can

be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,

while the remaining 15 cycles are executed in the background. Another pipeline

CSP

CPUCON1

CPUCON2

FIFO

IFU

IDX0

IDX1

QX1

QX0

QR1

QR0

SPSEG

VECSEG

STKOV

STKUN

DPP0

DPP1

DPP3

DPP2

+/-

ADU

MDL

MDH

MAL

Division Unit

MAH

Multiply Unit

MSW

MCW

ALU

+/-

Zeros

PSW

Ones

MRW

TFR

CPUID

MDC

Barrel-Shifter

Bit-Mask-Gen.

Multiply Unit

MAC

CPU

Buffer

2-Stage

Prefetch

Pipeline

5-Stage

Pipeline

IPIP

DPRAM

data in

data out

DMU

R15

R14

GPRs

R15

R14

GPRs

R15

R14

GPRs

R15

R14

GPRs

SRAM

address

Peripheral-Bus

PMU

Internal Program Memory

System-Bus

Prefetch Unit

Branch Unit

Return Stack

Injection/Exception

Handler

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