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PM0073 Fiches technique(PDF) 30 Page - STMicroelectronics |
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PM0073 Fiches technique(HTML) 30 Page - STMicroelectronics |
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30 / 34 page ![]() Register descriptions PM0073 30/34 Doc ID 17766 Rev 5 3.8 Write protection register (FLASH_WRPR) Address offset: 0x20 Reset value: 0xFFFF FFFF 3.9 Flash controller clock enable register (FLASH_CLKER) Address: 0x4000402C Reset value: 0x0000 0000 Note: This register is present in wireless line devices only. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRP[31:16] rr rr rr r r rr rr rr r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRP[15:0] rr rr rr r r rr rr rr r r Bits 31:0 WRP: Write protect This register contains the write-protection option bytes loaded by the OBL. 0: Write protection active 1: Write protection not active Note: These bits are read-only. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98765432 10 Reserved r/w Bits 31:1 Reserved, must be kept cleared. Bit 0 EN: Request enabling of FPEC_CLK. When set, FCLK is set to 12 MHz. |
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