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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AN4541 Fiches technique(PDF) 11 Page - STMicroelectronics |
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AN4541 Fiches technique(HTML) 11 Page - STMicroelectronics |
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11 / 21 page  DocID026513 Rev 1 11/21 AN4541 SD3.0 constrains 21 Figure 14. Data rate evaluation on the SD3.0 tested link The approximate 80 MB/s data rate in read and write mode is close to the specified value. Figure 15 shows the clock signal for measuring the rise and fall times. tR and tF are measured between 0.58 V and 1.27 V (VIL max and VIH min corresponding to VDD supply voltage): tR and tF are lower than 0.96 ns, the specified maximum value in the SD3.0 standard. Figure 15. Clock signal on the SD3.0 tested link To facilitate the testing of the protection device, an interface board is inserted between the card and the host (Figure 16). |
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