ADE7166_15 datasheet(103/152 Pages) AD

103 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 103 of 1

Table 95. LCD Segment Enable SFR (LCDSEGE, Address 0x97)

Bit

Mnemonic

Default

Description

FP25EN

FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP24EN

FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP23EN

FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP22EN

FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP21EN

FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP20EN

FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function.

[1:0]

Reserved

These bits must be kept at 0 for proper operation.

Table 96. LCD Pointer SFR (LCDPTR, Address 0xAC)

Bit

Mnemonic

Default

Description

R/W

Read or write LCD bit. If this bit is set to 1, the data in LCD data SFR (LCDDAT, Address 0xAE) is

written to the address indicated by the ADDRESS bits (LCDPTR, Address 0xAC).

Reserved

Reserved.

[5:0]

ADDRESS

LCD memory address (see Table 99).

Table 97. LCD Data SFR (LCDDAT, Address 0xAE)

Bit

Mnemonic

Default

Description

[7:0]

LCDDATA

Data to be written into or read out of the LCD memory SFRs.

Table 98. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)

Bit

Mnemonic

Default

Description

[7:4]

Reserved

Reserved.

FP19EN

FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP18EN

FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP17EN

FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP16EN

FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.

LCD SETUP

The LCD configuration SFR (LCDCON, Address 0x95)

configures the LCD module to drive the type of LCD in the user

end system. The BIAS bit (Bit 2) and the LMUX bits in this SFR

should be set according to the LCD specifications.

The COM2/FP28 and COM3/FP27 pins default to LCD segment

lines. Selecting the 3× multiplex level in the LCD configuration

SFR (LCDCON, Address 0x95) by setting LMUX[1:0] to 10

changes the FP28 pin functionality to COM2. The 4× multiplex

level selection, LMUX[1:0] = 11, changes the FP28 pin

functionality to COM2 and the FP27 pin functionality to

COM3.

The LCD segments of FP0 to FP15 and FP26 are enabled by

default. Additional pins are selected for LCD functionality in

the LCD segment enable SFR (LCDSEGE, Address 0x97) and

LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED) where

there are individual enable bits for the FP16 to FP25 segment

pins. The LCD pins do not have to be enabled sequentially. For

example, if the alternate function of FP23, the Timer 2 input, is

required, any of the other shared pins, FP16 to FP25, can be

enabled instead.

The Display Element Control section contains details about

setting up the LCD data memory to turn individual LCD

segments on and off. Setting the LCDRST bit (Bit 6) in the LCD

Configuration SFR (LCDCON, Address 0x95) resets the LCD

data memory to its default (0). A power-on reset also clears the

LCD data memory.

LCD TIMING AND WAVEFORMS

An LCD segment acts like a capacitor that is charged and

discharged at a certain rate. This rate, the refresh rate, determines

the visual characteristics of the LCD. A slow refresh rate results

in the LCD blinking on and off between refreshes. A fast refresh

rate presents a screen that appears to be continuously lit. In

addition, a faster refresh rate consumes more power.

The frame rate, or refresh rate, for the LCD module is derived

from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz

or 128 Hz by the CLKSEL bit (Bit 3) in the LCD Configuration

SFR (LCDCON, Address 0x95). The minimum refresh rate

needed for the LCD to appear solid (without blinking) is

independent of the multiplex level.

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