ADE7166_15 datasheet(68/152 Pages) AD

68 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 68 of

152

Reactive Power Gain Calibration

Figure 72 shows the signal processing chain for the ADE7169/

ADE7569 reactive power calculation. As explained in the

Reactive Power Calculation (ADE7169/ADE7569) section, the

reactive power is calculated by applying a low-pass filter to the

instantaneous reactive power signal. Note that, when reading

the waveform samples from the output of LPF2, the gain of the

reactive energy can be adjusted by using the multiplier and by

writing a twos complement, 12-bit word to the var gain register

(VARGAIN[11:0], Address 0x1E). Equation 25 shows how the

gain adjustment is related to the contents of the var gain register.

Output VARGAIN =

⎟

⎠

⎞

⎜

⎝

⎛

⎭

⎬

⎫

⎩

⎨

⎧ +

VARGAIN

Power

Reactive

(25)

The resolution of the VARGAIN register is the same as the

WGAIN register (see the Active Power Gain Calibration

section). VARGAIN can be used to calibrate the reactive

power (or energy) calculation in the ADE7169/ADE7569.

Reactive Power Offset Calibration

The ADE7169/ADE7569 also incorporate a reactive power

offset register (VAROS[15:0], Address 0x21). This signed, twos

complement, 16-bit register can be used to remove offsets in the

reactive power calculation (see Figure 72). An offset can exist in

the reactive power calculation due to crosstalk between channels

on the PCB or in the IC itself. The offset calibration allows the

contents of the reactive power register to be maintained at 0

when no power is being consumed.

The 256 LSBs (VAROS = 0x100) written to the reactive power

offset register are equivalent to 1 LSB in the WAVMODE register

(Address 0x0D).

Sign of Reactive Power Calculation

Note that the average reactive power is a signed calculation.

The phase shift filter has −90° phase shift when the integrator

is enabled, and +90° phase shift when the integrator is disabled.

Table 46 summarizes the relationship of the phase difference

between the voltage and the current and the sign of the resulting

var calculation.

Table 46. Sign of Reactive Power Calculation

Angle

Integrator

Sign

Between 0° to +90°

Off

Positive

Between −90° to 0°

Off

Negative

Between 0° to +90°

Positive

Between −90° to 0°

Negative

Reactive Power Sign Detection

The ADE7169/ADE7569 detect a change of sign in the reactive

power. The VARSIGN flag (Bit 4) in the Interrupt Status 1 SFR

(MIRQSTL, Address 0xDC) records when a change of sign has

occurred according to the VARSIGN bit (Bit 5) in the

ACCMODE register (Address 0x0F). If the VARSIGN bit is set

in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the

8052 core has a pending ADE interrupt. The ADE interrupt stays

active until the VARSIGN status bit is cleared (see the Energy

Measurement Interrupts section).

When VARSIGN (Bit 5) in the ACCMODE register (Address

0x0F) is cleared (default), the VARSIGN flag (Bit 4) in the

Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when

a transition from positive to negative reactive power occurs.

When VARSIGN in the ACCMODE register (Address 0x0F) is

set, the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL,

Address 0xDC) is set when a transition from negative to positive

reactive power occurs.

Reactive Power No Load Detection

The ADE7169/ADE7569 include a no load threshold feature on

the reactive energy that eliminates any creep effects in the

meter. The ADE7169/ADE7569 accomplish this by not

accumulating reactive energy when the multiplier output is

below the no load threshold. When the reactive power is below

the no load threshold, the RNOLOAD flag (Bit 1) in the Interrupt

Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the RNOLOAD

bit (Bit 1) is set in the Interrupt Enable 1 SFR (MIRQENL,

Address 0xD9), the 8052 core has a pending ADE interrupt. The

ADE interrupt stays active until the RNOLOAD status bit is

cleared (see the Energy Measurement Interrupts section).

The no load threshold level is selectable by setting the

VARNOLOAD bits (Bits[3:2]) in the NLMODE register

(Address 0x0E). Setting these bits to 0b00 disables the no load

detection, and setting them to 0b01, 0b10, or 0b11 sets the no

load detection threshold to 0.015%, 0.0075%, and 0.0037% of

the full-scale output frequency of the multiplier, respectively.

REACTIVE ENERGY CALCULATION

(ADE7169/ADE7569)

As for active energy, the ADE7169/ADE7569 achieve the

integration of the reactive power signal by continuously

accumulating the reactive power signal in an internal, nonreadable,

49-bit energy register. The reactive energy register (VARHR[23:0],

Address 0x04) represents the upper 24 bits of this internal

the ADE7169/ADE7569 only.

The discrete time sample period (T) for the accumulation register

in the ADE7169/ADE7569 is 1.22 μs (5/MCLK). As well as

calculating the energy, this integration removes any sinusoidal

components that may be in the active power signal. Figure 72

shows this discrete time integration or accumulation. The

reactive power signal in the waveform register is continuously

added to the internal reactive energy register.

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