ADE7166_15 datasheet(53/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 53 of

152

Voltage Channel ADC

Figure 48 shows the ADC and signal processing chain for the

voltage channel. In waveform sampling mode, the ADC outputs

a signed, twos complement, 24-bit data-word at a maximum

of 25.6 kSPS (MCLK/160). The ADC produces an output code

that is approximately between 0x28F5 (+10,485d) and 0xD70B

(−10,485d).

Channel Sampling

The waveform samples of the current ADC and voltage ADC

can also be routed to the waveform registers to be read by the

MCU core. The active, reactive, and apparent power and energy

calculation remain uninterrupted during waveform sampling.

When in waveform sampling mode, one of four output sample

rates can be chosen by using the DTRT[1:0] bits of the

WAVMODE register (see Table 35). The output sample rate can

be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM

enable bit is set in the Interrupt Enable 3 SFR (MIRQENH,

Address 0xDB), the 8052 core has a pending ADE interrupt.

The sampled signals selected in the WAVMODE register are

latched into the waveform SFRs when the waveform high byte

(WAV1H or WAV2H) is read.

The ADE interrupt stays active until the WFSM status bit is

cleared (see the Energy Measurement Interrupts section).

ANALOG

INPUT

RANGE

HPF

ADC

REFERENCE

0.5V, 0.25V,

0.125V, 62.5mV,

31.3mV

VOLTAGE RMS (Vrms)

CALCULATION

PGA2

VOLTAGE CHANNEL

WAVEFORM

DATA RANGE

0xD70B

0x0000

0x28F5

ACTIVE AND REACTIVE

POWER CALCULATION

LPF1

f–3dB = 63.7Hz

MODE 1[6]

ZX SIGNAL

DATA RANGE FOR 60Hz SIGNAL

0xE230

0x0000

0x1DD0

ZX DETECTION

ZX SIGNAL

DATA RANGE FOR 50Hz SIGNAL

0xDFC9

0x0000

0x2037

VOLTAGE PEAK DETECT

×1, ×2, ×4,

×8, ×16

{GAIN[7:5]}

WAVEFORM SAMPLE

Figure 48. ADC and Signal Processing in Voltage Channel

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