AT91SAM_14 datasheet(17/50 Pages) ATMEL

No de pièce	AT91SAM

Description	High-performance 32-bit RISC Architecture

PDF	50 Pages

Scroll/Zoom	100%

Fabricant	ATMEL [ATMEL Corporation]

Site Internet	http://www.atmel.com

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SAM7S Series [DATASHEET]

6175KS–ATARM–25-Oct-12

7.4

Peripheral DMA Controller

Handles data transfer between peripherals and memories

Eleven channels: SAM7S512/256/128/64/321/161

Nine channels: SAM7S32/16

Two for each USART

Two for the Debug Unit

Two for the Serial Synchronous Controller

Two for the Serial Peripheral Interface

One for the Analog-to-digital Converter

Low bus arbitration overhead

One Master Clock cycle needed for a transfer from memory to peripheral

Two Master Clock cycles needed for a transfer from peripheral to memory

Next Pointer management for reducing interrupt latency requirements

Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):

Receive

DBGU

Receive

USART0

Receive

USART1

Receive

SSC

Receive

ADC

Receive

SPI

Transmit

DBGU

Transmit

USART0

Transmit

USART1

Transmit

SSC

Transmit

SPI

AT91SAM Fiches technique(PDF) 17 Page - ATMEL Corporation