AM79C981 datasheet(18/40 Pages) AMD

18 / 40 page

AMD

PRELIMINARY

1–88

Am79C981

P Partitioning Status. This bit is 0 if the AUI port is

partitioned and 1 if connected.

B Bit Rate Error. This bit is set to 1 if there has been

an instance of FIFO Overflow or Underflow,

caused by data received at the AUI port. This bit is

cleared when the status is read.

S SQE Test Status. This bit is set to 1 if SQE Test is

detected by the IMR+ chip. This bit is cleared

when the status is read. A MAU attached to a re-

peater must have SQE Test disabled. This bit is

set even if the AUI port is disabled or partitioned.

L Loop Back Error. The MAU attached to the AUI is

required to loopback data transmitted to DO onto

the DI circuit. If loopback carrier is not detected by

the IMR+ device, then this bit is set to 1 to report

this condition. This bit is cleared when the status is

read. For a repeater this is the only indication of a

broken or missing MAU.

Alternate AUI Port Status

SI data:

10001111

SO data:

PBSL0000

There are three further variations of the above com-

mand, allowing selective clearing of a combination of B,

S, and L bits. They are primarily included for use by the

HIMIB chip. These are:

Alternative 1.

SI data:

10001011

SO data:

PBSL0000

B is not cleared. S and L are cleared.

Alternative 2.

SI data:

10001101

SO data:

PBSL0000

S and L are not cleared. B is cleared.

Alternative 3.

SI data:

10001001

SO data:

PBSL0000

None of S, B and L are cleared.

TP Port Partitioning Status

SI data:

10000000

SO data:

P7.................P0

Pn = 0

TP port n partitioned

Pn = 1

TP port n connected

The partitioning Status of all eight TP ports are ac-

cessed by this command. If a port is disabled, reading it

partitioning status will indicate that it is connected.

Bit Rate Error Status of TP Ports

SI data:

10100000

SO data:

E7...............E0

This allows a single command to be used to report Bit

Rate Error condition (FIFO Overflow or Underflow) of all

Twisted Pair ports. The 8 bits of the output pattern corre-

spond to each of the 8 TP ports, with least significant bit

corresponding to port 0.

The status bit for a port is set to 1 if there has been an

instance when data received from that port has caused

a FIFO error.

All status bits stay set until the status is read.

Link Test Status of TP Ports

SI data:

11010000

SO data:

L7...............L0

Ln = 0

TP Port n in Link Test Fail

Ln = 1

TP Port n in Link Test Pass

The Link Test Status of all eight TP ports are accessed

by this command. A disabled port continues to report

correct Link Test Status. Re-enabling a disabled port

causes the port to be placed into Link Test Fail state.

This ensures that packet fragments received on the port

are not repeated to the rest of the network.

Receive Polarity Status of TP Ports

SI data:

11100000

SO data:

P7...............P0

Pn = 0

TP Port n Polarity Correct

Pn = 1

TP Port n Polarity Reversed

The statuses of all eight TP port polarities are accessed

with this command. The IMR+ chip has the ability to de-

tect and correct reversed polarity on the TP ports’

RXD+/– pins. If the polarity is detected as reversed for a

TP port, then the IMR+ chip will set the appropriate bit in

this command’s result byte only if the Polarity Reversal

Function is enabled for that port.

MJLP Status

SI data:

11110000

SO data:

M00000000

Each IMR+ chip contains an independent MAU Jabber

Lock Up Protection Timer. The timer is designed to in-

hibit the IMR+ device transmit function, if it has been

transmitting continuously for more than 65536 Bit

Times. The MJLP Status bit (M) is set to 1 if this

happens. This bit remains set and is only cleared when

the MJLP status is read by using this command.

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